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authorBrian Norris <computersforpeace@gmail.com>2012-09-25 05:40:55 +0200
committerDavid Woodhouse <David.Woodhouse@intel.com>2012-09-29 16:58:28 +0200
commite2d3a35ee427aaba99b6c68a56609ce276c51270 (patch)
treefdc7fb47876d0e2ecbb3f48f107425a905fde878 /arch/arm/configs/cpu9g20_defconfig
parentmtd: nand: decode Hynix MLC, 6-byte ID length (diff)
downloadlinux-e2d3a35ee427aaba99b6c68a56609ce276c51270.tar.xz
linux-e2d3a35ee427aaba99b6c68a56609ce276c51270.zip
mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F ID
Datasheets for the following Samsung NAND parts (both MLC and SLC) describe extensions to the Samsung 6-byte extended ID decoding table: K9GBG08U0A (MLC, 6-byte ID) K9GAG08U0F (MLC, 6-byte ID) K9FAG08U0M (SLC, 6-byte ID) The table found in K9GAG08U0F, p.44, contains a superset of the information found in other previous datasheets. This patch adds support for all of these chips, with 512B and 640B OOB sizes. It also changes the detection pattern such that this table applies to all Samsung 6-byte ID NAND, not just MLC. This is safe, according to the NAND parameter data I have collected: Note that nand_base.c does not yet support the bad block marker scheme defined for these chips (i.e., scan 1st and last page for BB markers). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'arch/arm/configs/cpu9g20_defconfig')
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