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| author | Haojian Zhuang <haojian.zhuang@marvell.com> | 2010-04-28 16:59:45 +0200 |
|---|---|---|
| committer | Eric Miao <eric.y.miao@gmail.com> | 2010-05-11 17:25:04 +0200 |
| commit | 66b196475031c748a5861390a4fadb915e14ccdc (patch) | |
| tree | eaad4bcc929f4a744bc41c6fe739ef5278105031 /arch/arm/configs | |
| parent | [ARM] mmp: update clock register function (diff) | |
| download | linux-66b196475031c748a5861390a4fadb915e14ccdc.tar.xz linux-66b196475031c748a5861390a4fadb915e14ccdc.zip | |
[ARM] mmp: enable L2 in mmp2
Enable Tauros2 L2 in mmp2. Tauros2 L2 is shared in Marvell ARM cores.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch/arm/configs')
| -rw-r--r-- | arch/arm/configs/mmp2_defconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig index 03f76cfc941c..db8936370b6b 100644 --- a/arch/arm/configs/mmp2_defconfig +++ b/arch/arm/configs/mmp2_defconfig @@ -246,6 +246,8 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_TAUROS2=y CONFIG_ARM_L1_CACHE_SHIFT=5 # CONFIG_ARM_ERRATA_411920 is not set CONFIG_COMMON_CLKDEV=y |