diff options
author | Dmitry Osipenko <digetx@gmail.com> | 2019-03-17 23:52:05 +0100 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2019-04-09 16:36:19 +0200 |
commit | 96446e21d6e9303cce0374af3f4012556dc501ce (patch) | |
tree | 2009e3125850cee95578c8761d634a58c1114bbe /arch/arm/firmware | |
parent | ARM: trusted_foundations: Support L2 cache maintenance (diff) | |
download | linux-96446e21d6e9303cce0374af3f4012556dc501ce.tar.xz linux-96446e21d6e9303cce0374af3f4012556dc501ce.zip |
ARM: trusted_foundations: Make prepare_idle call to take mode argument
The Trusted Foundations firmware call varies depending on the required
suspend-mode. Make the firmware API to take the mode argument in order
to expose all of the modes to firmware user.
Tested-by: Robert Yang <decatf@gmail.com>
Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/firmware')
-rw-r--r-- | arch/arm/firmware/trusted_foundations.c | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index d7ac05103a52..720904a43c00 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -67,9 +67,34 @@ static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) return 0; } -static int tf_prepare_idle(void) +static int tf_prepare_idle(unsigned long mode) { - tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr); + switch (mode) { + case TF_PM_MODE_LP0: + tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr); + break; + + case TF_PM_MODE_LP1: + tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr); + break; + + case TF_PM_MODE_LP1_NO_MC_CLK: + tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK, + cpu_boot_addr); + break; + + case TF_PM_MODE_LP2: + tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr); + break; + + case TF_PM_MODE_LP2_NOFLUSH_L2: + tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, + cpu_boot_addr); + break; + + default: + return -EINVAL; + } return 0; } |