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| author | Chao Xie <xiechao.mail@gmail.com> | 2012-07-31 08:13:12 +0200 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-08-16 10:16:27 +0200 |
| commit | 38f2e3772429f29a273a2ed7e95dd7a41f662f06 (patch) | |
| tree | 2cf21a73ab581cabc5b03a34464dec7ac1178007 /arch/arm/include/asm/hardware | |
| parent | ARM: cache: add cputype.h for tauros2 (diff) | |
| download | linux-38f2e3772429f29a273a2ed7e95dd7a41f662f06.tar.xz linux-38f2e3772429f29a273a2ed7e95dd7a41f662f06.zip | |
ARM: cache: add extra feature enable for tauros2
The extra feature may be used by SOCs are prefetch, burst8,
write buffer coalesce
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/include/asm/hardware')
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-tauros2.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h index 538f17ca905b..295e2e40151b 100644 --- a/arch/arm/include/asm/hardware/cache-tauros2.h +++ b/arch/arm/include/asm/hardware/cache-tauros2.h @@ -8,4 +8,7 @@ * warranty of any kind, whether express or implied. */ -extern void __init tauros2_init(void); +#define CACHE_TAUROS2_PREFETCH_ON (1 << 0) +#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1) + +extern void __init tauros2_init(unsigned int features); |