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| author | Catalin Marinas <catalin.marinas@arm.com> | 2013-03-26 23:35:04 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-04-03 17:45:49 +0200 |
| commit | 93dc68876b608da041fe40ed39424b0fcd5aa2fb (patch) | |
| tree | dcd4dc84c5a0da7ce4c1581b3ee6f81fdb969765 /arch/arm/include/asm/mmu_context.h | |
| parent | ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug ... (diff) | |
| download | linux-93dc68876b608da041fe40ed39424b0fcd5aa2fb.tar.xz linux-93dc68876b608da041fe40ed39424b0fcd5aa2fb.zip | |
ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down
all use of the old entries. This patch implements the erratum workaround
which consists of:
1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.
2. Send IPI to the CPUs that are running the same mm (and ASID) as the
one being invalidated (or all the online CPUs for global pages).
3. CPU receiving the IPI executes a DMB and CLREX (part of the exception
return code already).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/mmu_context.h')
| -rw-r--r-- | arch/arm/include/asm/mmu_context.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index 863a6611323c..a7b85e0d0cc1 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h @@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm); void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); #define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) +DECLARE_PER_CPU(atomic64_t, active_asids); + #else /* !CONFIG_CPU_HAS_ASID */ #ifdef CONFIG_MMU |