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authorWill Deacon <will.deacon@arm.com>2012-07-28 17:27:03 +0200
committerWill Deacon <will.deacon@arm.com>2012-08-23 12:35:51 +0200
commitf0d1bc47953743aef9d2ed5326bc5973a3db08ab (patch)
treeda83dfd3a4ec6e92da3401a0563072bdfb3afccc /arch/arm/include/asm
parentARM: perf: add devicetree bindings for 11MPcore, A5, A7 and A15 PMUs (diff)
downloadlinux-f0d1bc47953743aef9d2ed5326bc5973a3db08ab.tar.xz
linux-f0d1bc47953743aef9d2ed5326bc5973a3db08ab.zip
ARM: pmu: remove unused reservation mechanism
The PMU reservation mechanism was originally intended to allow OProfile and perf-events to co-ordinate over access to the CPU PMU. Since then, OProfile for ARM has moved to using perf as its backend, so the reservation code is no longer used. This patch removes the reservation code for the CPU PMU on ARM. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/pmu.h34
1 files changed, 0 insertions, 34 deletions
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 40d7dff8bc30..05e0401d7697 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -49,40 +49,6 @@ struct arm_pmu_platdata {
int (*runtime_suspend)(struct device *dev);
};
-#ifdef CONFIG_CPU_HAS_PMU
-
-/**
- * reserve_pmu() - reserve the hardware performance counters
- *
- * Reserve the hardware performance counters in the system for exclusive use.
- * Returns 0 on success or -EBUSY if the lock is already held.
- */
-extern int
-reserve_pmu(enum arm_pmu_type type);
-
-/**
- * release_pmu() - Relinquish control of the performance counters
- *
- * Release the performance counters and allow someone else to use them.
- */
-extern void
-release_pmu(enum arm_pmu_type type);
-
-#else /* CONFIG_CPU_HAS_PMU */
-
-#include <linux/err.h>
-
-static inline int
-reserve_pmu(enum arm_pmu_type type)
-{
- return -ENODEV;
-}
-
-static inline void
-release_pmu(enum arm_pmu_type type) { }
-
-#endif /* CONFIG_CPU_HAS_PMU */
-
#ifdef CONFIG_HW_PERF_EVENTS
/* The events for a given PMU register set. */