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author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-02-15 22:20:18 +0100 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-02-15 22:20:18 +0100 |
commit | 56012808f4d5606e401539f663d92009d964425b (patch) | |
tree | f3736a97725647393a2db7c95462d857115197ca /arch/arm/include | |
parent | Merge branch 'for-rmk/samsung3' of git://git.fluff.org/bjdooks/linux into dev... (diff) | |
parent | [ARM] orion5x: D-link DNS-323 revision A1 power LED (diff) | |
download | linux-56012808f4d5606e401539f663d92009d964425b.tar.xz linux-56012808f4d5606e401539f663d92009d964425b.zip |
Merge branch 'for-rmk' of git://git.marvell.com/orion into devel-stable
Conflicts:
arch/arm/Makefile
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/cacheflush.h | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 730aefcfbee3..c77d2fa1f6e5 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -154,16 +154,16 @@ * Please note that the implementation of these, and the required * effects are cache-type (VIVT/VIPT/PIPT) specific. * - * flush_cache_kern_all() + * flush_kern_all() * * Unconditionally clean and invalidate the entire cache. * - * flush_cache_user_mm(mm) + * flush_user_all() * * Clean and invalidate all user space cache entries * before a change of page tables. * - * flush_cache_user_range(start, end, flags) + * flush_user_range(start, end, flags) * * Clean and invalidate a range of cache entries in the * specified address space before a change of page tables. @@ -179,6 +179,20 @@ * - start - virtual start address * - end - virtual end address * + * coherent_user_range(start, end) + * + * Ensure coherency between the Icache and the Dcache in the + * region described by start, end. If you have non-snooping + * Harvard caches, you need to implement this function. + * - start - virtual start address + * - end - virtual end address + * + * flush_kern_dcache_area(kaddr, size) + * + * Ensure that the data held in page is written back. + * - kaddr - page address + * - size - region size + * * DMA Cache Coherency * =================== * |