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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-04 17:13:29 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-14 20:21:42 +0100 |
| commit | ff2e27ae0b17f53a6a289c87d325f706598f3788 (patch) | |
| tree | 1288f491bce11b3d8a6d48604fd00d68bea6eb98 /arch/arm/include | |
| parent | ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init (diff) | |
| download | linux-ff2e27ae0b17f53a6a289c87d325f706598f3788.tar.xz linux-ff2e27ae0b17f53a6a289c87d325f706598f3788.zip | |
ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt. Move this into the common GIC code.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/hardware/gic.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 48876a3fbda8..a82a77703544 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -33,6 +33,8 @@ #define GIC_DIST_SOFTINT 0xf00 #ifndef __ASSEMBLY__ +extern void __iomem *gic_cpu_base_addr; + void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |