diff options
| author | Nicolas Pitre <nico@cam.org> | 2005-11-06 15:42:37 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-11-06 15:42:37 +0100 |
| commit | b7ec479553b8755dd95ee988a957cbf2aef351dc (patch) | |
| tree | b2066a113c7e0bb1546564038c692f6f423315bf /arch/arm/kernel/entry-armv.S | |
| parent | [ARM] 3114/1: use ixp2000_reg_wrb in ixp2000 uengine loader (diff) | |
| download | linux-b7ec479553b8755dd95ee988a957cbf2aef351dc.tar.xz linux-b7ec479553b8755dd95ee988a957cbf2aef351dc.zip | |
[ARM] 3115/1: small optimizations to exception vector entry code
Patch from Nicolas Pitre
Since we know the value of cpsr on entry, we can replace the bic+orr with
a single eor. Also remove a possible result delay (at least on XScale).
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel/entry-armv.S')
| -rw-r--r-- | arch/arm/kernel/entry-armv.S | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index be439cab92c6..a511ec5b11a3 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -785,7 +785,7 @@ __kuser_helper_end: * SP points to a minimal amount of processor-private memory, the address * of which is copied into r0 for the mode specific abort handler. */ - .macro vector_stub, name, correction=0 + .macro vector_stub, name, mode, correction=0 .align 5 vector_\name: @@ -805,15 +805,14 @@ vector_\name: @ Prepare for SVC32 mode. IRQs remain disabled. @ mrs r0, cpsr - bic r0, r0, #MODE_MASK - orr r0, r0, #SVC_MODE + eor r0, r0, #(\mode ^ SVC_MODE) msr spsr_cxsf, r0 @ @ the branch table must immediately follow this code @ - mov r0, sp and lr, lr, #0x0f + mov r0, sp ldr lr, [pc, lr, lsl #2] movs pc, lr @ branch to handler in SVC mode .endm @@ -823,7 +822,7 @@ __stubs_start: /* * Interrupt dispatcher */ - vector_stub irq, 4 + vector_stub irq, IRQ_MODE, 4 .long __irq_usr @ 0 (USR_26 / USR_32) .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) @@ -846,7 +845,7 @@ __stubs_start: * Data abort dispatcher * Enter in ABT mode, spsr = USR CPSR, lr = USR PC */ - vector_stub dabt, 8 + vector_stub dabt, ABT_MODE, 8 .long __dabt_usr @ 0 (USR_26 / USR_32) .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) @@ -869,7 +868,7 @@ __stubs_start: * Prefetch abort dispatcher * Enter in ABT mode, spsr = USR CPSR, lr = USR PC */ - vector_stub pabt, 4 + vector_stub pabt, ABT_MODE, 4 .long __pabt_usr @ 0 (USR_26 / USR_32) .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) @@ -892,7 +891,7 @@ __stubs_start: * Undef instr entry dispatcher * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC */ - vector_stub und + vector_stub und, UND_MODE .long __und_usr @ 0 (USR_26 / USR_32) .long __und_invalid @ 1 (FIQ_26 / FIQ_32) |