diff options
| author | Dave Martin <dave.martin@linaro.org> | 2012-02-09 17:47:17 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2012-09-19 09:32:50 +0200 |
| commit | 80c59dafb1a9a86fa996e6e34d06b60567c925ca (patch) | |
| tree | 1f9d36e82f58102722e3c3075fa9f3b73968cf33 /arch/arm/kernel/head.S | |
| parent | ARM: opcodes: add __ERET/__MSR_ELR_HYP instruction encoding (diff) | |
| download | linux-80c59dafb1a9a86fa996e6e34d06b60567c925ca.tar.xz linux-80c59dafb1a9a86fa996e6e34d06b60567c925ca.zip | |
ARM: virt: allow the kernel to be entered in HYP mode
This patch does two things:
* Ensure that asynchronous aborts are masked at kernel entry.
The bootloader should be masking these anyway, but this reduces
the damage window just in case it doesn't.
* Enter svc mode via exception return to ensure that CPU state is
properly serialised. This does not matter when switching from
an ordinary privileged mode ("PL1" modes in ARMv7-AR rev C
parlance), but it potentially does matter when switching from a
another privileged mode such as hyp mode.
This should allow the kernel to boot safely either from svc mode or
hyp mode, even if no support for use of the ARM Virtualization
Extensions is built into the kernel.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm/kernel/head.S')
| -rw-r--r-- | arch/arm/kernel/head.S | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 3db960e20cb8..27093e4feef8 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -83,8 +83,12 @@ ENTRY(stext) THUMB( .thumb ) @ switch to Thumb now. THUMB(1: ) - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode - @ and irqs disabled +#ifdef CONFIG_ARM_VIRT_EXT + bl __hyp_stub_install +#endif + @ ensure svc mode and all interrupts masked + safe_svcmode_maskall r9 + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type @ r5=procinfo r9=cpuid movs r10, r5 @ invalid processor (r5=0)? @@ -326,7 +330,11 @@ ENTRY(secondary_startup) * the processor type - there is no need to check the machine type * as it has already been validated by the primary processor. */ - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 +#ifdef CONFIG_ARM_VIRT_EXT + bl __hyp_stub_install +#endif + safe_svcmode_maskall r9 + mrc p15, 0, r9, c0, c0 @ get processor id bl __lookup_processor_type movs r10, r5 @ invalid processor? |