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authorWill Deacon <will.deacon@arm.com>2012-07-28 17:27:03 +0200
committerWill Deacon <will.deacon@arm.com>2012-08-23 12:35:51 +0200
commitf0d1bc47953743aef9d2ed5326bc5973a3db08ab (patch)
treeda83dfd3a4ec6e92da3401a0563072bdfb3afccc /arch/arm/kernel/perf_event.c
parentARM: perf: add devicetree bindings for 11MPcore, A5, A7 and A15 PMUs (diff)
downloadlinux-f0d1bc47953743aef9d2ed5326bc5973a3db08ab.tar.xz
linux-f0d1bc47953743aef9d2ed5326bc5973a3db08ab.zip
ARM: pmu: remove unused reservation mechanism
The PMU reservation mechanism was originally intended to allow OProfile and perf-events to co-ordinate over access to the CPU PMU. Since then, OProfile for ARM has moved to using perf as its backend, so the reservation code is no longer used. This patch removes the reservation code for the CPU PMU on ARM. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/kernel/perf_event.c')
-rw-r--r--arch/arm/kernel/perf_event.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 3aa338849133..1ac1531dcfef 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -377,7 +377,6 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
}
pm_runtime_put_sync(&pmu_device->dev);
- release_pmu(armpmu->type);
}
static int
@@ -391,12 +390,6 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
if (!pmu_device)
return -ENODEV;
- err = reserve_pmu(armpmu->type);
- if (err) {
- pr_warning("unable to reserve pmu\n");
- return err;
- }
-
plat = dev_get_platdata(&pmu_device->dev);
if (plat && plat->handle_irq)
handle_irq = armpmu_platform_irq;
@@ -706,7 +699,6 @@ static void __init cpu_pmu_init(struct arm_pmu *armpmu)
raw_spin_lock_init(&events->pmu_lock);
}
armpmu->get_hw_events = armpmu_get_cpu_events;
- armpmu->type = ARM_PMU_DEVICE_CPU;
}
/*