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authorWill Deacon <will.deacon@arm.com>2011-06-03 18:40:15 +0200
committerWill Deacon <will.deacon@arm.com>2011-07-07 20:20:53 +0200
commit0c205cbe20654616e2f8389c0c1ff707d9dccb63 (patch)
treebff2cc25f48b911faac970f5c0b98b6a795509e9 /arch/arm/kernel/perf_event.c
parentARM: perf: add PMUv2 common event definitions (diff)
downloadlinux-0c205cbe20654616e2f8389c0c1ff707d9dccb63.tar.xz
linux-0c205cbe20654616e2f8389c0c1ff707d9dccb63.zip
ARM: perf: add support for the Cortex-A5 PMU
This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event backend. Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/kernel/perf_event.c')
-rw-r--r--arch/arm/kernel/perf_event.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index d53c0abc4dd3..df4e517687bf 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -660,6 +660,9 @@ init_hw_perf_events(void)
case 0xC090: /* Cortex-A9 */
armpmu = armv7_a9_pmu_init();
break;
+ case 0xC050: /* Cortex-A5 */
+ armpmu = armv7_a5_pmu_init();
+ break;
}
/* Intel CPUs [xscale]. */
} else if (0x69 == implementor) {