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| author | Will Deacon <will.deacon@arm.com> | 2011-06-03 18:38:49 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2011-07-07 20:20:53 +0200 |
| commit | 7b35fa47eecd0c746924a6d6c2a897d2cec778ba (patch) | |
| tree | 0de0f06074ea375106feea2251d0f6389d963742 /arch/arm/kernel/perf_event_v7.c | |
| parent | ARM: proc: add proc info for Cortex-A15MP using classic page tables (diff) | |
| download | linux-7b35fa47eecd0c746924a6d6c2a897d2cec778ba.tar.xz linux-7b35fa47eecd0c746924a6d6c2a897d2cec778ba.zip | |
ARM: perf: remove confusing comment from v7 perf events backend
The comment about measuring TLB misses and refills in the ARMv7 perf
backend makes little sense and refers loosely to raw counters that
should be used instead.
This patch removes the comments to avoid any confusion.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/kernel/perf_event_v7.c')
| -rw-r--r-- | arch/arm/kernel/perf_event_v7.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 4960686afb58..554eba3dbf65 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -207,11 +207,6 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, }, [C(DTLB)] = { - /* - * Only ITLB misses and DTLB refills are supported. - * If users want the DTLB refills misses a raw counter - * must be used. - */ [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, @@ -323,11 +318,6 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] }, }, [C(DTLB)] = { - /* - * Only ITLB misses and DTLB refills are supported. - * If users want the DTLB refills misses a raw counter - * must be used. - */ [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, |