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| author | Ard Biesheuvel <ardb@kernel.org> | 2022-01-24 19:28:58 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ardb@kernel.org> | 2022-01-25 09:53:52 +0100 |
| commit | 75fa4adc4f50ee52d8cdfa3e84798176ccb4a354 (patch) | |
| tree | 138883d819bf540c067dd986ef505460e49376e9 /arch/arm/kernel | |
| parent | ARM: assembler: define a Kconfig symbol for group relocation support (diff) | |
| download | linux-75fa4adc4f50ee52d8cdfa3e84798176ccb4a354.tar.xz linux-75fa4adc4f50ee52d8cdfa3e84798176ccb4a354.zip | |
ARM: smp: elide HWCAP_TLS checks or __entry_task updates on SMP+v6
Use the SMP_ON_UP patching framework to elide HWCAP_TLS tests from the
context switch and return to userspace code paths, as SMP systems are
guaranteed to have this h/w capability.
At the same time, omit the update of __entry_task if the system is
detected to be UP at runtime, as in that case, the value is never used.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Diffstat (limited to 'arch/arm/kernel')
| -rw-r--r-- | arch/arm/kernel/entry-header.S | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index cb82ff5adec1..9a1dc142f782 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -292,21 +292,18 @@ .macro restore_user_regs, fast = 0, offset = 0 -#if defined(CONFIG_CPU_32v6K) || defined(CONFIG_SMP) -#if defined(CONFIG_CPU_V6) && defined(CONFIG_SMP) -ALT_SMP(b .L1_\@ ) -ALT_UP( nop ) - ldr_va r1, elf_hwcap - tst r1, #HWCAP_TLS @ hardware TLS available? - beq .L2_\@ -.L1_\@: +#if defined(CONFIG_CPU_32v6K) && \ + (!defined(CONFIG_CPU_V6) || defined(CONFIG_SMP)) +#ifdef CONFIG_CPU_V6 +ALT_SMP(nop) +ALT_UP_B(.L1_\@) #endif @ The TLS register update is deferred until return to user space so we @ can use it for other things while running in the kernel - get_thread_info r1 + mrc p15, 0, r1, c13, c0, 3 @ get current_thread_info pointer ldr r1, [r1, #TI_TP_VALUE] mcr p15, 0, r1, c13, c0, 3 @ set TLS register -.L2_\@: +.L1_\@: #endif uaccess_enable r1, isb=0 |