diff options
| author | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2015-01-15 15:59:26 +0100 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2015-01-16 18:07:25 +0100 |
| commit | a63ba4114690cad6e71cbcfd187b0ebf20321dfa (patch) | |
| tree | f4970ed6c4b3749ba1bad9532e6a41b95c992c14 /arch/arm/mach-at91/pm.c | |
| parent | ARM: at91: pm: use the mmio-sram pool to access SRAM (diff) | |
| download | linux-a63ba4114690cad6e71cbcfd187b0ebf20321dfa.tar.xz linux-a63ba4114690cad6e71cbcfd187b0ebf20321dfa.zip | |
ARM: at91: pm: add UDP and UHP checks to newer SoCs
Check UDP and UHP on sam9x5, sam9n12 and the sama5 series.
Check UHP on the sam9g45.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/pm.c')
| -rw-r--r-- | arch/arm/mach-at91/pm.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 515791edcc60..71cc845263dc 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -275,6 +275,7 @@ static int __init at91_pm_init(void) pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC; + at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; if (of_machine_is_compatible("atmel,at91rm9200")) { /* @@ -286,14 +287,8 @@ static int __init at91_pm_init(void) at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; at91_pm_data.memctrl = AT91_MEMCTRL_MC; - } else if (of_machine_is_compatible("atmel,at91sam9260") || - of_machine_is_compatible("atmel,at91sam9g20") || - of_machine_is_compatible("atmel,at91sam9261") || - of_machine_is_compatible("atmel,at91sam9g10") || - of_machine_is_compatible("atmel,at91sam9263")) { - at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | - AT91SAM926x_PMC_UDP; } else if (of_machine_is_compatible("atmel,at91sam9g45")) { + at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP; at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; } |