summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-at91rm9200/gpio.c
diff options
context:
space:
mode:
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-11-23 12:41:32 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-11-30 13:24:47 +0100
commit10dd5ce28d78e2440e8fa1135d17e33399d75340 (patch)
treed2e76765a57e7e47a9c424f99c3a22bf99c6da64 /arch/arm/mach-at91rm9200/gpio.c
parent[ARM] 3894/1: pxa27x: Update DCSR_EORINTR bit definition in DCSR (diff)
downloadlinux-10dd5ce28d78e2440e8fa1135d17e33399d75340.tar.xz
linux-10dd5ce28d78e2440e8fa1135d17e33399d75340.zip
[ARM] Remove compatibility layer for ARM irqs
set_irq_chipdata -> set_irq_chip_data get_irq_chipdata -> get_irq_chip_data do_level_IRQ -> handle_level_irq do_edge_IRQ -> handle_edge_irq do_simple_IRQ -> handle_simple_irq irqdesc -> irq_desc irqchip -> irq_chip Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91rm9200/gpio.c')
-rw-r--r--arch/arm/mach-at91rm9200/gpio.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index 7467d644f0a3..cec3862651d0 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -332,10 +332,10 @@ static struct irq_chip gpio_irqchip = {
.set_wake = gpio_irq_set_wake,
};
-static void gpio_irq_handler(unsigned irq, struct irqdesc *desc)
+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
unsigned pin;
- struct irqdesc *gpio;
+ struct irq_desc *gpio;
void __iomem *pio;
u32 isr;
@@ -396,7 +396,7 @@ void __init at91_gpio_irq_setup(void)
__raw_writel(~0, controller + PIO_IDR);
set_irq_data(id, (void *) pin);
- set_irq_chipdata(id, controller);
+ set_irq_chip_data(id, controller);
for (i = 0; i < 32; i++, pin++) {
/*
@@ -404,7 +404,7 @@ void __init at91_gpio_irq_setup(void)
* shorter, and the AIC handles interupts sanely.
*/
set_irq_chip(pin, &gpio_irqchip);
- set_irq_handler(pin, do_simple_IRQ);
+ set_irq_handler(pin, handle_simple_irq);
set_irq_flags(pin, IRQF_VALID);
}