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| author | Anton Vorontsov <avorontsov@mvista.com> | 2011-07-06 14:45:09 +0200 |
|---|---|---|
| committer | Anton Vorontsov <avorontsov@mvista.com> | 2011-07-07 16:48:38 +0200 |
| commit | 93e85d8e902e1a4468c6ade5c6ec3dd3055a489f (patch) | |
| tree | d6ee8fdc4609b35f7b903d9b1e8cb07f4abe12db /arch/arm/mach-cns3xxx/cns3420vb.c | |
| parent | ARM: cns3xxx: Should select CPU_V6K (diff) | |
| download | linux-93e85d8e902e1a4468c6ade5c6ec3dd3055a489f.tar.xz linux-93e85d8e902e1a4468c6ade5c6ec3dd3055a489f.zip | |
ARM: cns3xxx: Add support for L2 Cache Controller
CNS3xxx SOCs have L310-compatible cache controller, so let's use it.
With this patch benchmarking with 'gzip' shows that performance is
doubled, and I'm still able to boot full-fledged userland over NFS
(using PCIe NIC), so the support should be pretty robust.
p.s. While CNS3xxx reports that it has PL310, it still needs to wait
on cache line operations, so we should not select 'CACHE_PL310',
which is a micro-optimization that removes these waits for v7 CPUs.
Someday we'd better rename CACHE_PL310 Kconfig option into
NO_CACHE_WAIT or something less ambiguous.
Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
Diffstat (limited to 'arch/arm/mach-cns3xxx/cns3420vb.c')
| -rw-r--r-- | arch/arm/mach-cns3xxx/cns3420vb.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index 08e5c8759502..4b804baa5f80 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -170,6 +170,8 @@ static struct platform_device *cns3420_pdevs[] __initdata = { static void __init cns3420_init(void) { + cns3xxx_l2x0_init(); + platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); cns3xxx_ahci_init(); |