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| author | Krzysztof Hałasa <khalasa@piap.pl> | 2014-03-04 11:50:35 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2014-03-17 15:33:20 +0100 |
| commit | 75efba81513133fdd2f9c1ac9213bf86cc622f62 (patch) | |
| tree | 1f4edf6dfa5a0fe9873b4371321da40eaea025a3 /arch/arm/mach-cns3xxx/cns3420vb.c | |
| parent | Merge tag 'omap-for-v3.15/fixes-for-merge-window' of git://git.kernel.org/pub... (diff) | |
| download | linux-75efba81513133fdd2f9c1ac9213bf86cc622f62.tar.xz linux-75efba81513133fdd2f9c1ac9213bf86cc622f62.zip | |
CNS3xxx: Fix a WARN() related to IRQ allocation.
WARNING: at drivers/irqchip/irq-gic.c:952 gic_init_bases+0xe4/0x2b8()
Cannot allocate irq_descs @ IRQ16, assuming pre-allocated
Backtrace:
gic_init_bases from cns3xxx_init_irq+0x24/0x34
cns3xxx_init_irq from init_IRQ+0x24/0x2c
init_IRQ from start_kernel+0x1a8/0x338
start_kernel from 0x2000806c
The problem is that 64 CNS3xxx CPU interrupts, starting at 32, are
allocated by the ARM platform-independent code (as requested by
machine_desc->nr_irqs = 96), and then the GIC code tries to allocate
them again.
Tested on Gateworks Laguna board, masqueraded as CNS3420VB.
Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-cns3xxx/cns3420vb.c')
| -rw-r--r-- | arch/arm/mach-cns3xxx/cns3420vb.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index ce096d678aa4..d863d8729edc 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -246,7 +246,6 @@ static void __init cns3420_map_io(void) MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") .atag_offset = 0x100, - .nr_irqs = NR_IRQS_CNS3XXX, .map_io = cns3420_map_io, .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, |