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| author | Sandeep Paulraj <s-paulraj@ti.com> | 2009-07-27 15:57:07 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-08-26 10:55:49 +0200 |
| commit | a0f0202e2a19d43d733e07cb435a3064324c2ba7 (patch) | |
| tree | bfe505df91d1434ad2afd83f3edb0eb75e6d13b3 /arch/arm/mach-davinci/dma.c | |
| parent | DaVinci: EDMA: Add queue 2 and 3 for DM365 and DM6467 (diff) | |
| download | linux-a0f0202e2a19d43d733e07cb435a3064324c2ba7.tar.xz linux-a0f0202e2a19d43d733e07cb435a3064324c2ba7.zip | |
DaVinci: EDMA: Updating default queue handling
EDMA queues in DM365 are a little different than those
on other DaVinci's. On DM365 Q0 and Q1 have the larger
FIFO size. We want Q0 and Q1 to be used by codecs and
DVSDK demos.
MMC driver is the only driver which uses the flag
'EVENTQ_DEFAULT'. So MMC driver should be using Q2 instead of
Q1 on DM365.
This patch allows us to declare a "default queue" from
SOC specific code. If it is not declared then the EDMA
driver assumes a default of queue 1.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/dma.c')
| -rw-r--r-- | arch/arm/mach-davinci/dma.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 5908f7717b29..e6d7e6aca336 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -225,6 +225,7 @@ struct edma { unsigned num_slots; unsigned num_tc; unsigned num_cc; + enum dma_event_q default_queue; /* list of channels with no even trigger; terminated by "-1" */ const s8 *noevent; @@ -267,7 +268,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no, /* default to low priority queue */ if (queue_no == EVENTQ_DEFAULT) - queue_no = EVENTQ_1; + queue_no = edma_info[ctlr]->default_queue; queue_no &= 7; edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), @@ -1249,6 +1250,10 @@ static int __init edma_probe(struct platform_device *pdev) edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC); + edma_info[j]->default_queue = info[j].default_queue; + if (!edma_info[j]->default_queue) + edma_info[j]->default_queue = EVENTQ_1; + dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[j]); |