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authorCyril Chemparathy <cyril@ti.com>2010-05-07 23:06:38 +0200
committerKevin Hilman <khilman@deeprootsystems.com>2010-05-13 19:05:29 +0200
commit779b0d53ca41873d59225eb776c5d4493a0abd0f (patch)
treecf47ab5746105d9116e6c9e33f7ad142ff726d7a /arch/arm/mach-davinci/mux.c
parentDavinci: aintc/cpintc - use ioremap() (diff)
downloadlinux-779b0d53ca41873d59225eb776c5d4493a0abd0f.tar.xz
linux-779b0d53ca41873d59225eb776c5d4493a0abd0f.zip
Davinci: pinmux - use ioremap()
This patch modifies the pinmux implementation so as to ioremap() the pinmux register area on first use. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/mux.c')
-rw-r--r--arch/arm/mach-davinci/mux.c17
1 files changed, 12 insertions, 5 deletions
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index e9d530a8f79f..f34a8dcdae2b 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -22,6 +22,8 @@
#include <mach/mux.h>
#include <mach/common.h>
+static void __iomem *pinmux_base;
+
/*
* Sets the DAVINCI MUX register based on the table
*/
@@ -29,14 +31,19 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
{
static DEFINE_SPINLOCK(mux_spin_lock);
struct davinci_soc_info *soc_info = &davinci_soc_info;
- void __iomem *base = soc_info->pinmux_base;
unsigned long flags;
const struct mux_config *cfg;
unsigned int reg_orig = 0, reg = 0;
unsigned int mask, warn = 0;
- if (!soc_info->pinmux_pins)
- BUG();
+ if (WARN_ON(!soc_info->pinmux_pins))
+ return -ENODEV;
+
+ if (!pinmux_base) {
+ pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K);
+ if (WARN_ON(!pinmux_base))
+ return -ENOMEM;
+ }
if (index >= soc_info->pinmux_pins_num) {
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
@@ -57,7 +64,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
unsigned tmp1, tmp2;
spin_lock_irqsave(&mux_spin_lock, flags);
- reg_orig = __raw_readl(base + cfg->mux_reg);
+ reg_orig = __raw_readl(pinmux_base + cfg->mux_reg);
mask = (cfg->mask << cfg->mask_offset);
tmp1 = reg_orig & mask;
@@ -69,7 +76,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
if (tmp1 != tmp2)
warn = 1;
- __raw_writel(reg, base + cfg->mux_reg);
+ __raw_writel(reg, pinmux_base + cfg->mux_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}