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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-01-05 14:24:33 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-01-05 14:24:33 +0100 |
| commit | 2e0e943436912ffe0848ece58167edfe754edb96 (patch) | |
| tree | b91919095c74742fa06e2105db6d859bee39b2b4 /arch/arm/mach-exynos/cpu.c | |
| parent | Merge branches 'fixes' and 'misc' into for-linus (diff) | |
| parent | ARM: 7269/1: mach-sa1100: fix sched_clock breakage (diff) | |
| download | linux-2e0e943436912ffe0848ece58167edfe754edb96.tar.xz linux-2e0e943436912ffe0848ece58167edfe754edb96.zip | |
Merge branch 'devel-stable' into for-linus
Conflicts:
arch/arm/kernel/setup.c
arch/arm/mach-shmobile/board-kota2.c
Diffstat (limited to 'arch/arm/mach-exynos/cpu.c')
| -rw-r--r-- | arch/arm/mach-exynos/cpu.c | 20 |
1 files changed, 3 insertions, 17 deletions
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c index cc8d4bd6d0f7..699774cbf112 100644 --- a/arch/arm/mach-exynos/cpu.c +++ b/arch/arm/mach-exynos/cpu.c @@ -15,6 +15,7 @@ #include <asm/mach/irq.h> #include <asm/proc-fns.h> +#include <asm/exception.h> #include <asm/hardware/cache-l2x0.h> #include <asm/hardware/gic.h> @@ -33,8 +34,6 @@ #include <mach/regs-irq.h> #include <mach/regs-pmu.h> -unsigned int gic_bank_offset __read_mostly; - extern int combiner_init(unsigned int combiner_nr, void __iomem *base, unsigned int irq_start); extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); @@ -202,27 +201,14 @@ void __init exynos4_init_clocks(int xtal) exynos4_setup_clocks(); } -static void exynos4_gic_irq_fix_base(struct irq_data *d) -{ - struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); - - gic_data->cpu_base = S5P_VA_GIC_CPU + - (gic_bank_offset * smp_processor_id()); - - gic_data->dist_base = S5P_VA_GIC_DIST + - (gic_bank_offset * smp_processor_id()); -} - void __init exynos4_init_irq(void) { int irq; + unsigned int gic_bank_offset; gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; - gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); - gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base; - gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base; - gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base; + gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset); for (irq = 0; irq < MAX_COMBINER_NR; irq++) { |