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author | Sascha Hauer <s.hauer@pengutronix.de> | 2011-04-19 08:33:45 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-05-02 12:08:13 +0200 |
commit | b75c015143a4a6021731ff3e36718896381be94f (patch) | |
tree | 120a964bf4213ac2180c03f138f0e749253b4db2 /arch/arm/mach-imx/clk.h | |
parent | ARM: imx: add common clock support for pllv3 (diff) | |
download | linux-b75c015143a4a6021731ff3e36718896381be94f.tar.xz linux-b75c015143a4a6021731ff3e36718896381be94f.zip |
ARM i.MX: Add common clock support for 2bit gate
This gate consists of two bits:
0b00: clk disabled
0b01: clk enabled in run mode and disabled in sleep mode
0b11: clk enabled
Currently only disabled and enabled are supported. As it's unlikely
that we find something like this in another SoC create a i.MX specific
clk helper for this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-imx/clk.h')
-rw-r--r-- | arch/arm/mach-imx/clk.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index 331316d6a4de..5f6e435da4ae 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -24,6 +24,18 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 gate_mask, u32 div_mask); +struct clk *clk_register_gate2(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); + +static inline struct clk *imx_clk_gate2(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + shift, 0, &imx_ccm_lock); +} + static inline struct clk *imx_clk_fixed(const char *name, int rate) { return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); |