summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-imx/gpc.c
diff options
context:
space:
mode:
authorMarc Zyngier <marc.zyngier@arm.com>2014-12-02 17:05:26 +0100
committerOlof Johansson <olof@lixom.net>2014-12-05 08:24:51 +0100
commit65bb688aab9424849e94f74d555542fa76cd3d5a (patch)
tree97a06e6f2400b1719748d29e732f8d13ce4ba33e /arch/arm/mach-imx/gpc.c
parentARM: imx: irq: fix buggy usage of irq_data irq field (diff)
downloadlinux-65bb688aab9424849e94f74d555542fa76cd3d5a.tar.xz
linux-65bb688aab9424849e94f74d555542fa76cd3d5a.zip
ARM: imx6: fix bogus use of irq_get_irq_data
The imx6 PM code seems to be quite creative in its use of irq_data, using something that is very much a hardware interrupt number where we expect a virtual one. Yes, it worked so far, but that's only luck, and it will definitely explode in 3.19. Fix it by using a pair of helper functions that deal with the actual hardware. Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-imx/gpc.c')
-rw-r--r--arch/arm/mach-imx/gpc.c34
1 files changed, 22 insertions, 12 deletions
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 1455829c735e..5f3602ec74fa 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -91,34 +91,44 @@ void imx_gpc_restore_all(void)
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}
-void imx_gpc_irq_unmask(struct irq_data *d)
+void imx_gpc_hwirq_unmask(unsigned int hwirq)
{
void __iomem *reg;
u32 val;
- /* Sanity check for SPI irq */
- if (d->hwirq < 32)
- return;
-
- reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
+ reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
val = readl_relaxed(reg);
- val &= ~(1 << d->hwirq % 32);
+ val &= ~(1 << hwirq % 32);
writel_relaxed(val, reg);
}
-void imx_gpc_irq_mask(struct irq_data *d)
+void imx_gpc_hwirq_mask(unsigned int hwirq)
{
void __iomem *reg;
u32 val;
+ reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+ val = readl_relaxed(reg);
+ val |= 1 << (hwirq % 32);
+ writel_relaxed(val, reg);
+}
+
+static void imx_gpc_irq_unmask(struct irq_data *d)
+{
+ /* Sanity check for SPI irq */
+ if (d->hwirq < 32)
+ return;
+
+ imx_gpc_hwirq_unmask(d->hwirq);
+}
+
+static void imx_gpc_irq_mask(struct irq_data *d)
+{
/* Sanity check for SPI irq */
if (d->hwirq < 32)
return;
- reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
- val = readl_relaxed(reg);
- val |= 1 << (d->hwirq % 32);
- writel_relaxed(val, reg);
+ imx_gpc_hwirq_mask(d->hwirq);
}
void __init imx_gpc_init(void)