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authorShawn Guo <shawn.guo@linaro.org>2012-12-04 15:55:13 +0100
committerShawn Guo <shawn.guo@linaro.org>2013-01-30 14:08:34 +0100
commit485863b8fa02d515e48ce6b59f01d62172d2fe0d (patch)
treea5c6d41091969282e7b34208b191138a76326a7c /arch/arm/mach-imx/gpc.c
parentARM: imx: return zero in case next event gets a large increment (diff)
downloadlinux-485863b8fa02d515e48ce6b59f01d62172d2fe0d.tar.xz
linux-485863b8fa02d515e48ce6b59f01d62172d2fe0d.zip
ARM: imx: mask gpc interrupts initially
Mask gpc interrupts initially to avoid suspicious interrupts. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/gpc.c')
-rw-r--r--arch/arm/mach-imx/gpc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index e1537f9e45b8..722e5df7e44e 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -101,11 +101,16 @@ static void imx_gpc_irq_mask(struct irq_data *d)
void __init imx_gpc_init(void)
{
struct device_node *np;
+ int i;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
gpc_base = of_iomap(np, 0);
WARN_ON(!gpc_base);
+ /* Initially mask all interrupts */
+ for (i = 0; i < IMR_NUM; i++)
+ writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
+
/* Register GPC as the secondary interrupt controller behind GIC */
gic_arch_extn.irq_mask = imx_gpc_irq_mask;
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;