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author | Shawn Guo <shawn.guo@linaro.org> | 2013-10-16 13:52:00 +0200 |
---|---|---|
committer | Shawn Guo <shawn.guo@linaro.org> | 2013-10-21 03:39:26 +0200 |
commit | d48866fefdac239a4e02777e712aad60db9ee8a8 (patch) | |
tree | be0bb666ba9a8d0c29a262407e885ee91abb85e7 /arch/arm/mach-imx/pm-imx6q.c | |
parent | ARM: imx6q: call WB and RBC configuration from imx6q_pm_enter() (diff) | |
download | linux-d48866fefdac239a4e02777e712aad60db9ee8a8.tar.xz linux-d48866fefdac239a4e02777e712aad60db9ee8a8.zip |
ARM: imx: ensure dsm_request signal is not asserted when setting LPM
There is a defect in imx6 LPM design. When SW tries to enter low power
mode with following sequence, the chip will enter low power mode before
A9 CPU execute WFI instruction:
1. Set CCM_CLPCR[1:0] to 2'b00;
2. ARM CPU enters WFI;
3. ARM CPU wakeup from an interrupt event, which is masked by GPC or not
visible to GPC, such as interrupt from local timer;
4. Set CCM_CLPCR[1:0] to 2'b01 or 2'b10;
5. ARM CPU execute WFI.
Before the last step, the chip will enter WAIT mode if CCM_CLPCR[1:0] is
set to 2'b01, or enter STOP mode if CCM_CLPCR[1:0] is set to 2'b10.
The patch implements a recommended workaround for this issue.
1. SW triggers irq #32(IOMUX) to be always pending manually by setting
IOMUX_GPR1_GINT bit;
2. SW should then unmask it in GPC before setting CCM LPM;
3. SW should mask it right after CCM LPM is set (bit0-1 of CCM_CLPCR).
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/pm-imx6q.c')
-rw-r--r-- | arch/arm/mach-imx/pm-imx6q.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index fb7d90d36672..f303b56f087c 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -13,8 +13,12 @@ #include <linux/delay.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/irq.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/regmap.h> #include <linux/suspend.h> #include <asm/cacheflush.h> #include <asm/proc-fns.h> @@ -116,6 +120,7 @@ static void imx6q_enable_wb(bool enable) int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) { + struct irq_desc *iomuxc_irq_desc; u32 val = readl_relaxed(ccm_base + CLPCR); val &= ~BM_CLPCR_LPM; @@ -144,7 +149,16 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) return -EINVAL; } + /* + * Unmask the always pending IOMUXC interrupt #32 as wakeup source to + * deassert dsm_request signal, so that we can ensure dsm_request + * is not asserted when we're going to write CLPCR register to set LPM. + * After setting up LPM bits, we need to mask this wakeup source. + */ + iomuxc_irq_desc = irq_to_desc(32); + imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data); writel_relaxed(val, ccm_base + CLPCR); + imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data); return 0; } @@ -193,8 +207,20 @@ void __init imx6q_pm_set_ccm_base(void __iomem *base) void __init imx6q_pm_init(void) { + struct regmap *gpr; + WARN_ON(!ccm_base); + /* + * Force IOMUXC irq pending, so that the interrupt to GPC can be + * used to deassert dsm_request signal when the signal gets + * asserted unexpectedly. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, + IMX6Q_GPR1_GINT); + /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); |