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authorAnson Huang <Anson.Huang@nxp.com>2016-08-22 17:53:25 +0200
committerShawn Guo <shawnguo@kernel.org>2016-08-30 13:23:17 +0200
commit8aade778f787305fdbfd3c1d54e6b583601b5902 (patch)
tree2d242da6ee4454ecfc93907566b4aaba461948b0 /arch/arm/mach-imx
parentARM: dts: imx7d-sdb: fix ti,x-plate-ohms property name (diff)
downloadlinux-8aade778f787305fdbfd3c1d54e6b583601b5902.tar.xz
linux-8aade778f787305fdbfd3c1d54e6b583601b5902.zip
ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sx
i.MX6SX has bypass PMIC ready function, as this function is normally NOT enabled on the board design, so we need to bypass the PMIC ready pin check during DSM mode resume flow, otherwise, the internal DSM resume logic will be waiting for this signal to be ready forever and cause resume fail. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Fixes: ff843d621bfc ("ARM: imx: add suspend support for i.mx6sx") Cc: <stable@vger.kernel.org> Tested-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/pm-imx6.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 67bab74fcbc5..fe708e26d021 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -310,7 +310,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
val |= 0x3 << BP_CLPCR_STBY_COUNT;
val |= BM_CLPCR_VSTBY;
val |= BM_CLPCR_SBYOS;
- if (cpu_is_imx6sl())
+ if (cpu_is_imx6sl() || cpu_is_imx6sx())
val |= BM_CLPCR_BYPASS_PMIC_READY;
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;