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| author | Dan Williams <dan.j.williams@intel.com> | 2007-02-13 17:13:04 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-17 16:04:53 +0100 |
| commit | 4434c5c7fd61c6713de882a2272b66f32fe7cac3 (patch) | |
| tree | f20c9c4eba18dd915f07185cee5ededf33e28c02 /arch/arm/mach-iop33x/irq.c | |
| parent | [ARM] 4185/2: entry: introduce get_irqnr_preamble and arch_ret_to_user (diff) | |
| download | linux-4434c5c7fd61c6713de882a2272b66f32fe7cac3.tar.xz linux-4434c5c7fd61c6713de882a2272b66f32fe7cac3.zip | |
[ARM] 4186/1: iop: remove cp6_enable/disable routines
This functionality is replaced by cp6_trap
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop33x/irq.c')
| -rw-r--r-- | arch/arm/mach-iop33x/irq.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index effbe6b782d0..c65ea78a2427 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c @@ -24,44 +24,32 @@ static u32 iop33x_mask1; static inline void intctl0_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intctl1_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intstr0_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intstr1_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intbase_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static inline void intsize_write(u32 val) { - iop3xx_cp6_enable(); asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); - iop3xx_cp6_disable(); } static void |