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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-28 00:55:54 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-03-28 00:55:54 +0200 |
| commit | c8bc5e39ac110acc88e41dd45d3f99956686f074 (patch) | |
| tree | 1e4c21347e6d7b3cd7ac649436bbf3e2c1854229 /arch/arm/mach-lpc32xx/include | |
| parent | Merge tag 'stable/for-linus-3.4-tag-two' of git://git.kernel.org/pub/scm/linu... (diff) | |
| parent | Merge branch 'fixes' into next/fixes-non-critical (diff) | |
| download | linux-c8bc5e39ac110acc88e41dd45d3f99956686f074.tar.xz linux-c8bc5e39ac110acc88e41dd45d3f99956686f074.zip | |
Merge tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: Non-critical bug fixes" from Ardn Bergmann:
"Simple bug fixes that were not considered important enough for
inclusion into 3.3. One bug fix was originally intended for 3.3 but
accidentally got missed, but is not marked stable because it should
only get backported once later fixes also make it into v3.4.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>"
* tag 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (66 commits)
iomux-mx25.h slew rate adjusted for LCD __LD pins
ARM: davinci: DA850: move da850_register_pm to .init.text
ARM: davinci: cpufreq: fix compiler warning
ARM: OMAP2+: Fix build for omap4 only builds with missing include of linux/bug.h
ARM: OMAP2+: Fix section warnings for hsmmc_init_one
ARM: OMAP2+: Fix build issues with missing include of linux/bug.h
ARM: OMAP2+: gpmc-smsc911x: only register regulator for first instance
ARM: OMAP3+: PM: VP: fix integer truncation error
ARM: OMAP2+: PM: fix wakeupgen warning when hotplug disabled
ARM: OMAP2+: PM: fix section mismatch with omap2_init_processor_devices()
ARM: OMAP2: Fix section warning for n8x0 when CONFIG_MMC_OMAP is not set
ARM: OMAP2+: Fix omap24xx_io_desc warning if SoC subtypes are not selected
ARM: OMAP1: Fix section mismatch for omap1_init_early()
ARM: OMAP1: Fix typo in lcd_dma.c
ARM: OMAP: mailbox: trivial whitespace fix
ARM: OMAP: Remove definition cpu_is_omap4430()
ARM: OMAP2+: included some headers twice
ARM: OMAP: clock.c: included linux/debugfs.h twice
ARM: OMAP: don't build hwspinlock in vain
ARM: OMAP2+: ads7846_init: put gpio_pendown into pdata if it's provided
...
Diffstat (limited to 'arch/arm/mach-lpc32xx/include')
| -rw-r--r-- | arch/arm/mach-lpc32xx/include/mach/platform.h | 51 |
1 files changed, 27 insertions, 24 deletions
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h index 14ea8d1aadb5..c584f5bb164f 100644 --- a/arch/arm/mach-lpc32xx/include/mach/platform.h +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h @@ -591,42 +591,42 @@ /* * Timer/counter register offsets */ -#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00) -#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04) -#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08) -#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C) -#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10) -#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14) -#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18) -#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) -#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20) -#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24) -#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28) -#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) -#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30) -#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34) -#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38) -#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) -#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) +#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00) +#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04) +#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08) +#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C) +#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10) +#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14) +#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18) +#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) +#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20) +#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24) +#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28) +#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) +#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30) +#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34) +#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38) +#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) +#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) /* * ir register definitions */ -#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) -#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) +#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) +#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) /* * tcr register definitions */ -#define LCP32XX_TIMER_CNTR_TCR_EN 0x1 -#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2 +#define LPC32XX_TIMER_CNTR_TCR_EN 0x1 +#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2 /* * mcr register definitions */ -#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) -#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) -#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) +#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) +#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) +#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) /* * Standard UART register offsets @@ -690,5 +690,8 @@ #define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) #define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) #define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) +#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) +#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) +#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) #endif |