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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-18 18:12:14 +0200
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-04-18 18:12:14 +0200
commitfac56c2df51bc29b07b3c2dcfabf32a015a0522c (patch)
tree1ff5d84ecf4ea0bcbd42e2ef9624b5ade3810890 /arch/arm/mach-lpc32xx/pm.c
parentARM: s3c2440: gta02; Register dfbmcs320 device for BT audio interface (diff)
parentLinux 2.6.39-rc3 (diff)
downloadlinux-fac56c2df51bc29b07b3c2dcfabf32a015a0522c.tar.xz
linux-fac56c2df51bc29b07b3c2dcfabf32a015a0522c.zip
Merge commit 'v2.6.39-rc3' into for-2.6.39
Diffstat (limited to 'arch/arm/mach-lpc32xx/pm.c')
-rw-r--r--arch/arm/mach-lpc32xx/pm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index e76d41bb7056..b9c80597b7bf 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -41,7 +41,7 @@
* DRAM clocking and refresh are slightly different for systems with DDR
* DRAM or regular SDRAM devices. If SDRAM is used in the system, the
* SDRAM will still be accessible in direct-run mode. In DDR based systems,
- * a transistion to direct-run mode will stop all DDR accesses (no clocks).
+ * a transition to direct-run mode will stop all DDR accesses (no clocks).
* Because of this, the code to switch power modes and the code to enter
* and exit DRAM self-refresh modes must not be executed in DRAM. A small
* section of IRAM is used instead for this.