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authorLubomir Rintel <lkundrak@v3.sk>2019-06-26 23:42:19 +0200
committerLubomir Rintel <lkundrak@v3.sk>2019-10-17 16:36:11 +0200
commitd093bc0378f5e3542bfbbae0c0533ae68e260013 (patch)
tree6cd1cca8535ce9e73c3fae35d75aceee54a04346 /arch/arm/mach-mmp
parentARM: mmp: add support for MMP3 SoC (diff)
downloadlinux-d093bc0378f5e3542bfbbae0c0533ae68e260013.tar.xz
linux-d093bc0378f5e3542bfbbae0c0533ae68e260013.zip
ARM: mmp: add SMP support
Used to bring up the second core on MMP3. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Diffstat (limited to 'arch/arm/mach-mmp')
-rw-r--r--arch/arm/mach-mmp/Makefile3
-rw-r--r--arch/arm/mach-mmp/platsmp.c32
2 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 322c1c97dc90..7b3a7f979eec 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -22,6 +22,9 @@ ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
endif
+ifeq ($(CONFIG_SMP),y)
+obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o
+endif
# board support
obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
diff --git a/arch/arm/mach-mmp/platsmp.c b/arch/arm/mach-mmp/platsmp.c
new file mode 100644
index 000000000000..c99405469bb4
--- /dev/null
+++ b/arch/arm/mach-mmp/platsmp.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+#include <linux/io.h>
+#include <asm/smp_scu.h>
+#include <asm/smp.h>
+#include "addr-map.h"
+
+#define SW_BRANCH_VIRT_ADDR CIU_REG(0x24)
+
+static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ /*
+ * Apparently, the boot ROM on the second core spins on this
+ * register becoming non-zero and then jumps to the address written
+ * there. No IPIs involved.
+ */
+ __raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
+ return 0;
+}
+
+static void mmp3_smp_prepare_cpus(unsigned int max_cpus)
+{
+ scu_enable(SCU_VIRT_BASE);
+}
+
+static const struct smp_operations mmp3_smp_ops __initconst = {
+ .smp_prepare_cpus = mmp3_smp_prepare_cpus,
+ .smp_boot_secondary = mmp3_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);