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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-04 17:13:29 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-14 20:21:42 +0100 |
| commit | ff2e27ae0b17f53a6a289c87d325f706598f3788 (patch) | |
| tree | 1288f491bce11b3d8a6d48604fd00d68bea6eb98 /arch/arm/mach-msm | |
| parent | ARM: GIC: Remove MMIO address from gic_cpu_init, rename to gic_secondary_init (diff) | |
| download | linux-ff2e27ae0b17f53a6a289c87d325f706598f3788.tar.xz linux-ff2e27ae0b17f53a6a289c87d325f706598f3788.zip | |
ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt. Move this into the common GIC code.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-msm')
| -rw-r--r-- | arch/arm/mach-msm/board-msm8x60.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index aaf8ec8a1495..9b5eb2b4ae1b 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -28,8 +28,6 @@ #include <mach/board.h> #include <mach/msm_iomap.h> -void __iomem *gic_cpu_base_addr; - unsigned long clk_get_max_axi_khz(void) { return 0; @@ -44,8 +42,8 @@ static void __init msm8x60_init_irq(void) { unsigned int i; - gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE; - gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, gic_cpu_base_addr); + gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, + (void *)MSM_QGIC_CPU_BASE); /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); |