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| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2014-04-14 17:10:05 +0200 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2014-05-08 18:10:24 +0200 |
| commit | ccd6a13180193700067bfdac5f7d7b436d757382 (patch) | |
| tree | 4a65ee228f54af51b80a748ede961a68196a0cc1 /arch/arm/mach-mvebu/headsmp.S | |
| parent | ARM: mvebu: add Armada 38x compatible string to pmsu (diff) | |
| download | linux-ccd6a13180193700067bfdac5f7d7b436d757382.tar.xz linux-ccd6a13180193700067bfdac5f7d7b436d757382.zip | |
ARM: mvebu: remove the address parameter for ll_set_cpu_coherent
In order to be able to deal with the MMU enabled and the MMU disabled
cases, the base address of the coherency registers was passed to the
function. The address by itself was not interesting as it can't change
for a given SoC, the only thing we need is to have a distinction
between the physical or the virtual address.
This patch add a check of the MMU bit to choose the accurate address,
then the calling function doesn't have to pass this information.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/mach-mvebu/headsmp.S')
| -rw-r--r-- | arch/arm/mach-mvebu/headsmp.S | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S index 3dd80df428f7..f30bc8d78871 100644 --- a/arch/arm/mach-mvebu/headsmp.S +++ b/arch/arm/mach-mvebu/headsmp.S @@ -31,11 +31,6 @@ ENTRY(armada_xp_secondary_startup) ARM_BE8(setend be ) @ go BE8 if entered LE - /* Get coherency fabric base physical address */ - adr r0, 1f - ldr r1, [r0] - ldr r0, [r0, r1] - /* Read CPU id */ mrc p15, 0, r1, c0, c0, 5 and r1, r1, #0xF @@ -45,7 +40,3 @@ ENTRY(armada_xp_secondary_startup) b secondary_startup ENDPROC(armada_xp_secondary_startup) - - .align 2 -1: - .long coherency_phys_base - . |