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| author | Thomas Gleixner <tglx@linutronix.de> | 2022-06-07 16:11:14 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-06-10 14:51:35 +0200 |
| commit | 0fdebc5ec2ca492d69df2d93a6a7abade4941aae (patch) | |
| tree | b07a97e9aac2eeed3d434267ab05aa52b2bc01bf /arch/arm/mach-mvebu/platsmp.c | |
| parent | treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (pa... (diff) | |
| download | linux-0fdebc5ec2ca492d69df2d93a6a7abade4941aae.tar.xz linux-0fdebc5ec2ca492d69df2d93a6a7abade4941aae.zip | |
treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 1)
Based on the normalized pattern:
this file is licensed under the terms of the gnu general public
license version 2 this program is licensed as is without any warranty
of any kind whether express or implied
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm/mach-mvebu/platsmp.c')
| -rw-r--r-- | arch/arm/mach-mvebu/platsmp.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index c130497dc6cc..18384ea6862c 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Symmetric Multi Processing (SMP) support for Armada XP * @@ -8,10 +9,6 @@ * Gregory CLEMENT <gregory.clement@free-electrons.com> * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency * This file implements the routines for preparing the SMP infrastructure * and waking up the secondary CPUs |