diff options
| author | Richard Zhu <Hong-Xing.Zhu@freescale.com> | 2011-02-28 12:32:03 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-03-07 19:29:19 +0100 |
| commit | 359219025e20a3ad61f081a82e0feec0583aca9b (patch) | |
| tree | 560c563d32ea1e91839814480b54c137360e8ae4 /arch/arm/mach-mx5/crm_regs.h | |
| parent | arm: mxs: tx28: add i2c bus and connected RTC (diff) | |
| download | linux-359219025e20a3ad61f081a82e0feec0583aca9b.tar.xz linux-359219025e20a3ad61f081a82e0feec0583aca9b.zip | |
ARM: imx51/53: add sdhc3/4 clock
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx5/crm_regs.h')
| -rw-r--r-- | arch/arm/mach-mx5/crm_regs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index b462c22f53d8..87c0c58f27a7 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -217,9 +217,12 @@ #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19) #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) @@ -271,6 +274,10 @@ #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19) #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) |