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author | Tony Lindgren <tony@atomide.com> | 2012-10-02 21:39:09 +0200 |
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committer | Tony Lindgren <tony@atomide.com> | 2012-10-17 20:36:37 +0200 |
commit | 4c98dc6b8ef2f73bdbfa78186db9a76507ba9ea3 (patch) | |
tree | 2f9f897dc9f4b8c0923e955008460d9516f7dd00 /arch/arm/mach-omap1/board-perseus2.c | |
parent | Merge branch 'omap-for-v3.8/cleanup-headers-dss' into omap-for-v3.8/cleanup-h... (diff) | |
download | linux-4c98dc6b8ef2f73bdbfa78186db9a76507ba9ea3.tar.xz linux-4c98dc6b8ef2f73bdbfa78186db9a76507ba9ea3.zip |
ARM: OMAP: Make plat/fpga.h local to arch/arm/plat-omap
There's no need to have this file in plat/fpga.h. We can
make it local to plat-omap replacing fpga_read/write
functions directly with readb/writeb as that's how
they are already defined in fpga.h.
Note that 2420 based H4 is also using the fpga, so let's
keep the led support around in plat-omap until we flip
over mach-omap2 to device tree.
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: linux-fbdev@vger.kernel.org
Cc: Felipe Balbi <balbi@ti.com>
Cc: linux-usb@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap1/board-perseus2.c')
-rw-r--r-- | arch/arm/mach-omap1/board-perseus2.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 198b05417bfc..a1cdeeb43f46 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -30,7 +30,7 @@ #include <plat/tc.h> #include <mach/mux.h> -#include <plat/fpga.h> +#include <../plat-omap/fpga.h> #include <mach/flash.h> #include <mach/hardware.h> @@ -231,9 +231,9 @@ static struct omap_lcd_config perseus2_lcd_config __initdata = { static void __init perseus2_init_smc91x(void) { - fpga_write(1, H2P2_DBG_FPGA_LAN_RESET); + __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET); mdelay(50); - fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1, + __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1, H2P2_DBG_FPGA_LAN_RESET); mdelay(50); } |