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| author | Rajendra Nayak <rnayak@ti.com> | 2010-01-20 01:30:55 +0100 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2010-01-20 21:35:28 +0100 |
| commit | ecbb06594744b72c362cb2252cb5f6de7cf1b394 (patch) | |
| tree | 9073d78f6c122faf2831201189f108f1b263db16 /arch/arm/mach-omap1/clock.c | |
| parent | OMAP4: PRCM: Fix the base address for CHIRONSS reg defines (diff) | |
| download | linux-ecbb06594744b72c362cb2252cb5f6de7cf1b394.tar.xz linux-ecbb06594744b72c362cb2252cb5f6de7cf1b394.zip | |
OMAP4: clocks: Fix the clksel_rate struct DPLL divs
For all DPLL's the valid dividers are same as the values
to be programmed in the register. 0 is an invalid value.
The changes are generated by updating the script which autogenerates
the file modifed in the patch.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap1/clock.c')
0 files changed, 0 insertions, 0 deletions