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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-06-06 01:13:40 +0200 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-07-25 16:28:14 +0200 |
| commit | f746929ffdc8a83c0e6092343d4475f6485e13d3 (patch) | |
| tree | 3d8a782cdc5232e37dd21a7a3565d56a95b62080 /arch/arm/mach-omap2/Kconfig | |
| parent | ARM: add soc memory barrier extension (diff) | |
| download | linux-f746929ffdc8a83c0e6092343d4475f6485e13d3.tar.xz linux-f746929ffdc8a83c0e6092343d4475f6485e13d3.zip | |
Revert "ARM: OMAP4: remove dead kconfig option OMAP4_ERRATA_I688"
This reverts commit 606da4826b89b044b51e3a84958b802204cfe4c7.
We actually need this code for proper behaviour of OMAP4, and it needs
fixing a different way other than just removing the code. Disabling
code which is necessary in the hopes of persuing multiplatform kernels
is a stupid approach.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/Kconfig')
| -rw-r--r-- | arch/arm/mach-omap2/Kconfig | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index ecc04ff13e95..2128441430ad 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -240,6 +240,27 @@ config OMAP3_SDRC_AC_TIMING wish to say no. Selecting yes without understanding what is going on could result in system crashes; +config OMAP4_ERRATA_I688 + bool "OMAP4 errata: Async Bridge Corruption" + depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM + select ARCH_HAS_BARRIERS + help + If a data is stalled inside asynchronous bridge because of back + pressure, it may be accepted multiple times, creating pointer + misalignment that will corrupt next transfers on that data path + until next reset of the system (No recovery procedure once the + issue is hit, the path remains consistently broken). Async bridge + can be found on path between MPU to EMIF and MPU to L3 interconnect. + This situation can happen only when the idle is initiated by a + Master Request Disconnection (which is trigged by software when + executing WFI on CPU). + The work-around for this errata needs all the initiators connected + through async bridge must ensure that data path is properly drained + before issuing WFI. This condition will be met if one Strongly ordered + access is performed to the target right before executing the WFI. + In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. + IO barrier ensure that there is no synchronisation loss on initiators + operating on both interconnect port simultaneously. endmenu endif |