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authorWill Deacon <will.deacon@arm.com>2012-01-20 12:01:10 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-01-23 11:20:05 +0100
commita092f2b15399bb4d1aa4e83cffe775f0c946f323 (patch)
treeb32be39bb3823afbc01ad5f10774ec6a13c30934 /arch/arm/mach-omap2/Kconfig
parentARM: 7290/1: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary (diff)
downloadlinux-a092f2b15399bb4d1aa4e83cffe775f0c946f323.tar.xz
linux-a092f2b15399bb4d1aa4e83cffe775f0c946f323.zip
ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs
To ensure correct alignment of cacheline-aligned data, the maximum cacheline size needs to be known at compile time. Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely that there will be future ARMv7 implementations with the same line size) then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline size. For CPUs with smaller caches, this will result in some harmless padding but will help with single zImage work and avoid hitting subtle bugs with misaligned data structures. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/Kconfig')
-rw-r--r--arch/arm/mach-omap2/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index a8ba7b96dcd1..41e6612ecbaf 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -33,7 +33,6 @@ config ARCH_OMAP3
default y
select CPU_V7
select USB_ARCH_HAS_EHCI
- select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
select ARCH_HAS_OPP
select PM_OPP if PM
select ARM_CPU_SUSPEND if PM