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author | Jean-Sebastien A. Beaudry <jsabeaudry@handyem.com> | 2013-01-23 22:02:40 +0100 |
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committer | Tony Lindgren <tony@atomide.com> | 2013-02-01 23:50:18 +0100 |
commit | 14e067c1a5280fe6fe5d3348a0bae87bc4da16db (patch) | |
tree | 3f612a3c8f9bc0e33c0ab977fa45e9868e933f31 /arch/arm/mach-omap2/am33xx-restart.c | |
parent | Linux 3.8-rc6 (diff) | |
download | linux-14e067c1a5280fe6fe5d3348a0bae87bc4da16db.tar.xz linux-14e067c1a5280fe6fe5d3348a0bae87bc4da16db.zip |
ARM: OMAP2+: AM33xx: Add SoC specific restart hook
Add restart hook so that DTS based AM33xx builds can restart
the platform.
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Jean-Sebastien A. Beaudry <jsabeaudry@handyem.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/am33xx-restart.c')
-rw-r--r-- | arch/arm/mach-omap2/am33xx-restart.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c new file mode 100644 index 000000000000..88e4fa8af031 --- /dev/null +++ b/arch/arm/mach-omap2/am33xx-restart.c @@ -0,0 +1,34 @@ +/* + * am33xx-restart.c - Code common to all AM33xx machines. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> + +#include "common.h" +#include "prm-regbits-33xx.h" +#include "prm33xx.h" + +/** + * am3xx_restart - trigger a software restart of the SoC + * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c + * @cmd: passed from the userspace program rebooting the system (if provided) + * + * Resets the SoC. For @cmd, see the 'reboot' syscall in + * kernel/sys.c. No return value. + */ +void am33xx_restart(char mode, const char *cmd) +{ + /* TODO: Handle mode and cmd if necessary */ + + am33xx_prm_rmw_reg_bits(AM33XX_GLOBAL_WARM_SW_RST_MASK, + AM33XX_GLOBAL_WARM_SW_RST_MASK, + AM33XX_PRM_DEVICE_MOD, + AM33XX_PRM_RSTCTRL_OFFSET); + + /* OCP barrier */ + (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD, + AM33XX_PRM_RSTCTRL_OFFSET); +} |