diff options
author | Vaibhav Hiremath <hvaibhav@ti.com> | 2013-04-01 04:22:21 +0200 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2013-04-01 04:22:21 +0200 |
commit | da91b89eb76d4ecddcfc7fca3b8422891eb5e62e (patch) | |
tree | a24460a60ba3fd9f9ee1ae4fed8b9a3e53731b12 /arch/arm/mach-omap2/cclock33xx_data.c | |
parent | ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry (diff) | |
download | linux-da91b89eb76d4ecddcfc7fca3b8422891eb5e62e.tar.xz linux-da91b89eb76d4ecddcfc7fca3b8422891eb5e62e.zip |
ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
WDT1 module can take one of the below clocks as input functional
clock -
- On-Chip 32K RC Osc [default/reset]
- 32K from PRCM
The On-Chip 32K RC Osc clock is not an accurate clock-source as per
the design/spec, so as a result, for example, timer which supposed
to get expired @60Sec, but will expire somewhere ~@40Sec, which is
not expected by any use-case.
The solution here is to switch the input clock-source to PRCM
generated 32K clock-source during boot-time itself.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Benoit Cousson <benoit.cousson@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/cclock33xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/cclock33xx_data.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 476b82066cb6..7f091c85384e 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -958,6 +958,14 @@ int __init am33xx_clk_init(void) clk_set_parent(&timer3_fck, &sys_clkin_ck); clk_set_parent(&timer6_fck, &sys_clkin_ck); + /* + * The On-Chip 32K RC Osc clock is not an accurate clock-source as per + * the design/spec, so as a result, for example, timer which supposed + * to get expired @60Sec, but will expire somewhere ~@40Sec, which is + * not expected by any use-case, so change WDT1 clock source to PRCM + * 32KHz clock. + */ + clk_set_parent(&wdt1_fck, &clkdiv32k_ick); return 0; } |