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authorVaibhav Hiremath <hvaibhav@ti.com>2012-08-24 16:54:24 +0200
committerPaul Walmsley <paul@pwsan.com>2012-09-13 00:28:34 +0200
commit78da264019e18db25b937fbb98328c680b1161cd (patch)
tree10703621325d2c60fb982b8a2e3ebdf4f4c8f47d /arch/arm/mach-omap2/clkt_dpll.c
parentARM: OMAP3+: hwmod: Add AM33XX HWMOD data (diff)
downloadlinux-78da264019e18db25b937fbb98328c680b1161cd.tar.xz
linux-78da264019e18db25b937fbb98328c680b1161cd.zip
ARM: OMAP2+: dpll: Add missing soc_is_am33xx() check for common functions
Add missing soc_is_am33xx() check for DPLL common control & clock related functions, without this dpll programmability would be broken for am33xx family of devices. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clkt_dpll.c')
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index cd7fd0f91149..05ff99e528c8 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk)
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd->clk_bypass);
- } else if (cpu_is_omap44xx()) {
+ } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
return dd->clk_bypass->rate;
- } else if (cpu_is_omap44xx()) {
+ } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)