diff options
| author | Rajendra Nayak <rnayak@ti.com> | 2009-12-09 02:47:17 +0100 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-12-12 01:00:47 +0100 |
| commit | 911bd7395c4aa4e74b13aab790ca1500c59fae02 (patch) | |
| tree | 6fdca6b205015558663dcfa523f87d6c6ffa7afa /arch/arm/mach-omap2/clock.c | |
| parent | ARM: OMAP4: PM: Add support for OMAP4 dpll api's (diff) | |
| download | linux-911bd7395c4aa4e74b13aab790ca1500c59fae02.tar.xz linux-911bd7395c4aa4e74b13aab790ca1500c59fae02.zip | |
ARM: OMAP4: PM: Add init api for DPLL nodes
An api at init for all dpll nodes seem to be
needed to reparent the dpll clk node to its
bypass clk in case the dpll is in bypass.
If not done this causes sequencing issues at init
during propogate_rate.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock.c | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 61ee23596ea8..759c72a48f7f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -70,9 +70,41 @@ u8 cpu_mask; /*------------------------------------------------------------------------- - * OMAP2/3 specific clock functions + * OMAP2/3/4 specific clock functions *-------------------------------------------------------------------------*/ +void omap2_init_dpll_parent(struct clk *clk) +{ + u32 v; + struct dpll_data *dd; + + dd = clk->dpll_data; + if (!dd) + return; + + /* Return bypass rate if DPLL is bypassed */ + v = __raw_readl(dd->control_reg); + v &= dd->enable_mask; + v >>= __ffs(dd->enable_mask); + + /* Reparent in case the dpll is in bypass */ + if (cpu_is_omap24xx()) { + if (v == OMAP2XXX_EN_DPLL_LPBYPASS || + v == OMAP2XXX_EN_DPLL_FRBYPASS) + clk_reparent(clk, dd->clk_bypass); + } else if (cpu_is_omap34xx()) { + if (v == OMAP3XXX_EN_DPLL_LPBYPASS || + v == OMAP3XXX_EN_DPLL_FRBYPASS) + clk_reparent(clk, dd->clk_bypass); + } else if (cpu_is_omap44xx()) { + if (v == OMAP4XXX_EN_DPLL_LPBYPASS || + v == OMAP4XXX_EN_DPLL_FRBYPASS || + v == OMAP4XXX_EN_DPLL_MNBYPASS) + clk_reparent(clk, dd->clk_bypass); + } + return; +} + /** * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware * @clk: struct clk * |