diff options
| author | Paul Walmsley <paul@pwsan.com> | 2009-05-13 01:27:10 +0200 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-05-13 01:27:10 +0200 |
| commit | b7aee4bfa7cad909220491214037731c1edb510a (patch) | |
| tree | e8f01165e2e8b92e1eaef40badc6ad55f4dbb122 /arch/arm/mach-omap2/clock.c | |
| parent | OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz (diff) | |
| download | linux-b7aee4bfa7cad909220491214037731c1edb510a.tar.xz linux-b7aee4bfa7cad909220491214037731c1edb510a.zip | |
OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code
The CORE DPLL M2 frequency change code should use pr_debug(), not
pr_info(), for its debug messages. Same with
omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR ..
into pr_err().
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 4247a1534411..8935a8b26186 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -547,8 +547,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, const struct clksel_rate *clkr; u32 last_div = 0; - printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", - clk->name, target_rate); + pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", + clk->name, target_rate); *new_div = 1; @@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, /* Sanity check */ if (clkr->div <= last_div) - printk(KERN_ERR "clock: clksel_rate table not sorted " + pr_err("clock: clksel_rate table not sorted " "for clock %s", clk->name); last_div = clkr->div; @@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, } if (!clkr->div) { - printk(KERN_ERR "clock: Could not find divisor for target " + pr_err("clock: Could not find divisor for target " "rate %ld for clock %s parent %s\n", target_rate, clk->name, clk->parent->name); return ~0; @@ -582,8 +582,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, *new_div = clkr->div; - printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, - (clk->parent->rate / clkr->div)); + pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, + (clk->parent->rate / clkr->div)); return (clk->parent->rate / clkr->div); } |