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authorTero Kristo <t-kristo@ti.com>2013-10-22 10:47:08 +0200
committerMike Turquette <mturquette@linaro.org>2014-01-17 21:36:57 +0100
commit3ada6b10aaf2ff5c7dc6e8add6fdf1b7333d1b34 (patch)
tree477d264728d811e5c2738afb4ff2560bab71656a /arch/arm/mach-omap2/clock.c
parentARM: dts: am43xx clock data (diff)
downloadlinux-3ada6b10aaf2ff5c7dc6e8add6fdf1b7333d1b34.tar.xz
linux-3ada6b10aaf2ff5c7dc6e8add6fdf1b7333d1b34.zip
ARM: OMAP2+: clock: add support for indexed memmaps
Using indexed memmaps is required for isolating the actual memory access from the clock code. Now, the driver providing the support for the clock IP block provides the low level routines for reading/writing clock registers also. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
-rw-r--r--arch/arm/mach-omap2/clock.c26
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 238be3f1ddce..be53bb21301c 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -26,7 +26,6 @@
#include <linux/clk-private.h>
#include <asm/cpu.h>
-
#include <trace/events/power.h>
#include "soc.h"
@@ -56,6 +55,31 @@ u16 cpu_mask;
static bool clkdm_control = true;
static LIST_HEAD(clk_hw_omap_clocks);
+void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
+{
+ if (clk->flags & MEMMAP_ADDRESSING) {
+ struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+ writel_relaxed(val, clk_memmaps[r->index] + r->offset);
+ } else {
+ writel_relaxed(val, reg);
+ }
+}
+
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
+{
+ u32 val;
+
+ if (clk->flags & MEMMAP_ADDRESSING) {
+ struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+ val = readl_relaxed(clk_memmaps[r->index] + r->offset);
+ } else {
+ val = readl_relaxed(reg);
+ }
+
+ return val;
+}
/*
* Used for clocks that have the same value as the parent clock,