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| author | Richard Woodruff <r-woodruff2@ti.com> | 2010-02-23 06:09:08 +0100 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2010-02-24 20:15:02 +0100 |
| commit | 358965d7bab9c70c11b64931da02667b161cb03a (patch) | |
| tree | 884a13c783f9ba43cc5fe063c5fbeecde7804f58 /arch/arm/mach-omap2/clock34xx_data.c | |
| parent | ARM: OMAP4 clock domain: Add check for avoiding dependency related update. (diff) | |
| download | linux-358965d7bab9c70c11b64931da02667b161cb03a.tar.xz linux-358965d7bab9c70c11b64931da02667b161cb03a.zip | |
OMAP3 clock: introduce DPLL4 Jtype
DPLL4 for 3630 introduces a changed block called j type dpll, requiring
special divisor bits and additional reg fields. To allow for silicons to
use this, this is introduced as a flag and is enabled for 3630 silicon.
OMAP4 also has j type dpll for usb.
Tested with 3630 ZOOM3 and OMAP3430 ZOOM2
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
[paul@pwsan.com: added some comments; updated copyrights and credits; fixed
some style issues]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock34xx_data.c | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 8bb8134872ce..60c6140b86af 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -38,6 +38,7 @@ /* Maximum DPLL multiplier, divider values for OMAP3 */ #define OMAP3_MAX_DPLL_MULT 2048 +#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095 #define OMAP3_MAX_DPLL_DIV 128 /* @@ -529,7 +530,8 @@ static struct clk emu_core_alwon_ck = { /* DPLL4 */ /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ /* Type: DPLL */ -static struct dpll_data dpll4_dd = { +static struct dpll_data dpll4_dd; +static struct dpll_data dpll4_dd_34xx __initdata = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, @@ -552,6 +554,29 @@ static struct dpll_data dpll4_dd = { .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; +static struct dpll_data dpll4_dd_3630 __initdata = { + .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), + .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK, + .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), + .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, + .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, + .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, + .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), + .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, + .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), + .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, + .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, + .min_divider = 1, + .max_divider = OMAP3_MAX_DPLL_DIV, + .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE, + .flags = DPLL_J_TYPE +}; + static struct clk dpll4_ck = { .name = "dpll4_ck", .ops = &omap3_clkops_noncore_dpll_ops, @@ -3377,6 +3402,11 @@ int __init omap3xxx_clk_init(void) &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; } + if (cpu_is_omap3630()) + dpll4_dd = dpll4_dd_3630; + else + dpll4_dd = dpll4_dd_34xx; + clk_init(&omap2_clk_functions); for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++) |