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| author | Tero Kristo <t-kristo@ti.com> | 2015-02-27 16:54:14 +0100 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2015-06-02 11:30:58 +0200 |
| commit | f3b19aa5cab65f7e73613aa37f6851ce56b794d1 (patch) | |
| tree | d71464c084f3a7bb56568ae7291fe19561a8d222 /arch/arm/mach-omap2/clock3xxx.c | |
| parent | Linux 4.1-rc2 (diff) | |
| download | linux-f3b19aa5cab65f7e73613aa37f6851ce56b794d1.tar.xz linux-f3b19aa5cab65f7e73613aa37f6851ce56b794d1.zip | |
ARM: OMAP2+: clock: export driver API to setup/get clock features
As most of the clock driver support code is going to be moved under
drivers/clk/ti, an API for setting / getting the SoC specific clock
features is needed. This patch provides this API and changes the
existing code to use it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock3xxx.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index a9e86db5daf9..8bede6aec44f 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -58,7 +58,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, * on 3430ES1 prevents us from changing DPLL multipliers or dividers * on DPLL4. */ - if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) { + if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); return -EINVAL; } @@ -81,7 +81,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index) { - if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) { + if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) { pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n"); return -EINVAL; } |