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| author | Paul Walmsley <paul@pwsan.com> | 2011-02-25 23:49:53 +0100 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2011-02-26 00:10:42 +0100 |
| commit | c6461f5c5970833cf28c5096cdfc7a095eb3bbb5 (patch) | |
| tree | c4cc4f827c7282eae12669ca30230834bc84d34a /arch/arm/mach-omap2/clock3xxx_data.c | |
| parent | omap4: dpll: Enable auto gate control for all MX postdividers (diff) | |
| download | linux-c6461f5c5970833cf28c5096cdfc7a095eb3bbb5.tar.xz linux-c6461f5c5970833cf28c5096cdfc7a095eb3bbb5.zip | |
OMAP2+: clock: disable autoidle on all clocks during clock init
Disable autoidle on all clocks during clock framework initialization.
(If CONFIG_PM is set, autoidle is re-enabled for all clocks later in
the boot process.)
The principle behind this patch, and some similar patches, is that the
kernel should start with all power management features disabled.
Later in the boot process, the PM code, if compiled in with CONFIG_PM,
enables or re-enables power management features.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock3xxx_data.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 78ea7997686b..65b79e6afb53 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3538,6 +3538,9 @@ int __init omap3xxx_clk_init(void) omap2_init_clk_clkdm(c->lk.clk); } + /* Disable autoidle on all clocks; let the PM code enable it later */ + omap_clk_disable_autoidle_all(); + recalculate_root_clocks(); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", @@ -3551,7 +3554,8 @@ int __init omap3xxx_clk_init(void) clk_enable_init_clocks(); /* - * Lock DPLL5 and put it in autoidle. + * Lock DPLL5 -- here only until other device init code can + * handle this */ if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0)) omap3_clk_lock_dpll5(); |