diff options
| author | Rajendra Nayak <rnayak@ti.com> | 2012-04-04 18:20:01 +0200 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-04-04 22:52:49 +0200 |
| commit | 6c4a057bffe9823221eab547e11fac181dc18a2b (patch) | |
| tree | 7994b9f41bdc822aec2be715546affd60e6d5609 /arch/arm/mach-omap2/clock44xx_data.c | |
| parent | ARM: OMAP4: clock data: fix mult and div mask for USB_DPLL (diff) | |
| download | linux-6c4a057bffe9823221eab547e11fac181dc18a2b.tar.xz linux-6c4a057bffe9823221eab547e11fac181dc18a2b.zip | |
ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock
All DPLLs except USB are in ALWON powerdomain. Make sure the
clkdm/pwrdm for USB DPLL (l3init) is turned on before attempting
a DPLL relock. So, mark the database accordingly.
Without this fix, it was seen that DPLL relock fails while testing
relock in a loop of USB DPLL.
Cc: Nishanth Menon <nm@ti.com>
Tested-by: Ameya Palande <ameya.palande@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock44xx_data.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 984904fcd244..fa6ea65ad44b 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -978,6 +978,7 @@ static struct clk dpll_usb_ck = { .recalc = &omap3_dpll_recalc, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, + .clkdm_name = "l3_init_clkdm", }; static struct clk dpll_usb_clkdcoldo_ck = { |