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| author | Thara Gopinath <thara@ti.com> | 2009-12-09 00:33:15 +0100 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-12-12 01:00:42 +0100 |
| commit | 3863c74b512c1afd3ce6b2f81d8dea9f1d860968 (patch) | |
| tree | 1d7d15664c0ae3a71be7949e9c52ca2f79a73811 /arch/arm/mach-omap2/cm.c | |
| parent | OMAP3: SDRC: Place SDRC AC timing and MR changes in CORE DVFS SRAM code behin... (diff) | |
| download | linux-3863c74b512c1afd3ce6b2f81d8dea9f1d860968.tar.xz linux-3863c74b512c1afd3ce6b2f81d8dea9f1d860968.zip | |
OMAP3: PM: Fix for MPU power domain MEM BANK position
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath <thara@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/cm.c')
0 files changed, 0 insertions, 0 deletions