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| author | Grant Likely <grant.likely@secretlab.ca> | 2010-01-28 22:38:25 +0100 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2010-01-28 22:38:25 +0100 |
| commit | 0ada0a73120c28cc432bcdbac061781465c2f48f (patch) | |
| tree | d17cadd4ea47e25d9e48e7d409a39c84268fbd27 /arch/arm/mach-omap2/cm.h | |
| parent | of: unify phandle name in struct device_node (diff) | |
| parent | Linux 2.6.33-rc5 (diff) | |
| download | linux-0ada0a73120c28cc432bcdbac061781465c2f48f.tar.xz linux-0ada0a73120c28cc432bcdbac061781465c2f48f.zip | |
Merge commit 'v2.6.33-rc5' into secretlab/test-devicetree
Diffstat (limited to 'arch/arm/mach-omap2/cm.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm.h | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index cfd0b726ba44..90a4086fbdf4 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -4,8 +4,8 @@ /* * OMAP2/3 Clock Management (CM) register definitions * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation + * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley * @@ -17,11 +17,17 @@ #include "prcm-common.h" #define OMAP2420_CM_REGADDR(module, reg) \ - OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) + OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) #define OMAP2430_CM_REGADDR(module, reg) \ - OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) + OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) #define OMAP34XX_CM_REGADDR(module, reg) \ - OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) + OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) +#define OMAP44XX_CM1_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg)) +#define OMAP44XX_CM2_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg)) + +#include "cm44xx.h" /* * Architecture-specific global CM registers @@ -89,6 +95,11 @@ #define OMAP3430_CM_CLKSEL2_EMU 0x0050 #define OMAP3430_CM_CLKSEL3_EMU 0x0054 +/* CM2.CEFUSE_CM2 register offsets */ + +/* OMAP4 modulemode control */ +#define OMAP4430_MODULEMODE_HWCTRL 0 +#define OMAP4430_MODULEMODE_SWCTRL 1 /* Clock management domain register get/set */ |